01 / Photonic sensingResearch & concept development
ArtiSense
Exploring how light can reveal chemical information, with a miniaturized sensing system at the heart of the research.
Explore ArtiSenseResearch snapshot · 2026
Artifactory / What we do
Design with light.
Read the world.
Follow light from micro-optics into a photonic circuit, through sensing and electronic readout. Explore how optical design, electronics and micromechanics come together in one system.
Touch the light or heater. Drag empty space to turn the view.
Geometry & model
Native balanced MZI with two MMIs and an upper-arm heater. Ideal equal splitting and recombination: T = cos²(Δφ/2). The control sets relative heating power, 0–100%. A quasi-static thermal model gives temperature rise proportional to power and a thermo-optic phase change. The full range is normalized to twice the heating needed for a π shift at 850 nm; no watts or kelvin are claimed. The resulting phase scales with 850 nm / λ. The output phase uses the unheated path as reference. No calibrated voltage, temperature or insertion loss.
Input amplitude is an electric-field amplitude; input power is its square. Global input phase changes the output wave phase, not transmission. Output waveforms share a vertical scale; AWG outputs carry the indicated ×16 field magnification. Internal glow indicates propagation, not solved field intensity. Colors and animation speed are illustrative. The die is shown in an isometric projection of the native optical paths; its package and metal pads are illustrative. Light strokes and field probes are enlarged for visibility. AWG probe leaders are not additional CAD guides. Heater color indicates relative drive, not a calibrated temperature.
Explore Artifactory
Our projects
A path for light.
A response to matter.
From optical sensing to design across scales.
- ArtiSense
- Exploring optical responses for chemical sensing.
- AIFIELD
- Rooted in photonics. Expanding design across optics, electronics and mechanics — from millimetres to nanometres.
02 / Multiphysics designDevelopment & internal demonstrations
AIFIELD
A design and simulation environment rooted in photonics, expanding towards optical, electronic and mechanical systems — from millimetres through micrometres to nanometres.
Explore AIFIELDResearch snapshot · 2026
Conceptual illustration · not a product image or measured result
Across scales
From a moving microstructure
to a measurable signal.
Explore the connection between electrical drive, mechanical movement and optical routing in the AIFIELD design study.
Follow the connected designAcross disciplines / inside silicon
Light. Motion.
Logic.
A waveguide guides light. A transistor switches a signal. We connect these different scales of design, from optical elements to integrated circuits and the systems around them.
Micro-optics
Lenses, diffractive elements and coupling: shape where light goes and how it is distributed.
Photonics
Waveguides, interference and spectral circuits: guide light and shape its response.
Micro- & nanoelectronics
Targeting integrated-circuit (IC) design: device structures, circuit architectures and layout at micro- and nanoscales.
Explore the transistorsElectronics & PCB
Detectors, analogue readout, PCB and control: turn an optical response into useful data.
Micromechanics
Geometry, mounts, alignment and tolerances: bring the parts together so they can work as a system.
Interactive design studyTwo transistors.
Two transistors.
One inverted signal.
Touch the input. Follow the logic. Lift the metal to see what connects beneath.
01 / SILICONPlanar CMOS · complementary logic
ZOOM
Input 0 → PMOS on · NMOS off → output 1
INSPECT
Select a transistor in the artwork to trace its source, gate and drain.
PMOSSection through the gate · schematic
Illustrative drift; not a current simulation.
Drag to rotate · hold + scroll to zoom · pinch on touchscreens
Explore the layer stack
About this design study
Original, illustrative planar CMOS inverter: PMOS in an n-well, NMOS in a p-type substrate, with body ties to VDD and ground. Gates share the input; drains share the output. Contacts reach Metal 1; a via connects the output to Metal 2. Oxide is shown at the gates; isolation and interlayer dielectrics are omitted for visibility. Colours identify materials and logic states, not moving photons or measured current. Ideal binary switching only; dimensions and layer spacing are enlarged. Not a PDK-qualified layout, SPICE result, FinFET model or fabricated device.
Reference: CMOS layer terminology ↗Services
Technical support
for your team.
From a feasibility question to a design study or an engineering workflow, we help you define and carry out a focused scope of work.
Photonic design & simulation
Explore design alternatives and understand how a photonic system behaves before the next development step.
Explore this serviceOptical sensing & feasibility
Assess whether an optical measurement approach can address your sensing problem.
Explore this serviceEngineering workflows & automation
Make recurring design and analysis tasks easier to run, inspect and repeat.
Explore this serviceValidation planning & technical review
Establish what to test, what to compare against and what would count as useful evidence.
Explore this serviceResearch & development
What has been
investigated?
Review design examples, simulation comparisons and open questions. These research records distinguish model outputs from physical measurements.
How we work
From a design question
to the next experiment.
ArtiSense provides a sensing question; AIFIELD helps explore possible designs. Our approach keeps the assumptions, results and remaining uncertainties connected.
See how we workDefine the question
Start with a measurement or design objective and the conditions you want to investigate.
Model and inspect
Examine geometry, assumptions and simulation outputs, with an engineer responsible for interpretation.
Plan the next test
Identify what the model has not established and the physical experiment needed to investigate it.
Start a conversation
Tell us what you
want to investigate.
Tell us about your technical goal, the constraints you are working with and the outputs you need.